发明名称 |
ENABLING MAXIMUM CONCURRENCY IN A HYBRID TRANSACTIONAL MEMORY SYSTEM |
摘要 |
In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed. |
申请公布号 |
EP3123306(A1) |
申请公布日期 |
2017.02.01 |
申请号 |
EP20150768457 |
申请日期 |
2015.03.25 |
申请人 |
Intel Corporation |
发明人 |
CALCIU, Irina;GOTTSCHLICH, Justin E.;SHPEISMAN, Tatiana;POKAM, Gilles A. |
分类号 |
G06F9/38;G06F17/30 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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