发明名称 半導体装置
摘要 The invention provides a semiconductor device which suppresses the increasing of substrate layers and ensures the characteristics of a transmission line. A first bus terminal group on a memory side and a first bus terminal groups, electrically connected with second relay terminal group, on a controller side on first and second memories are arranged in such a manner that the bit number increasing directions are set as opposite to each other. The first bus terminal group on the memory side IS electrically connected with a first relay terminal group of the second relay terminal group connected on a wiring substrate through wiring patterns. A second bus terminal group on the memory side of the first and second memory chips of the third relay terminal electrically connected on the wiring substrate and a second bus terminal group, electrically connected to the third relay terminal group, on the memory side are arranged in such a manner that the bit number increasing directions are set as same directions. The first memory chip is arranged on the wiring substrate, the second memory chip is arranged on the first memory chip, and a control chip is arranged on the second memory chip.
申请公布号 JP6071929(B2) 申请公布日期 2017.02.01
申请号 JP20140049743 申请日期 2014.03.13
申请人 株式会社東芝 发明人 片岡 忠
分类号 H01L25/065;G06F12/00;G06F13/16;H01L25/07;H01L25/18 主分类号 H01L25/065
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