Disturb-proof static RAM cells

摘要

A circuit includes a latch circuit, a buffer transistor having a control terminal coupled to a first output of the latch, a first write transistor having a conduction terminal coupled to the first output and a control terminal coupled to a first write bitline, and a second write transistor having a conduction terminal coupled to a second output of the latch and a control terminal coupled to a second write bitline. A method of operating a memory cell circuit includes providing a first value on first and second write bitlines when a read operation is performed, and when a write operation is performed, providing first and second values on the first and second write bitlines, respectively, when a first storable value is to be stored, and providing the first and second value on the second and first write bitlines, respectively, when a second storable value is to be stored.

主权项

1. A circuit comprising:
a latch circuit; a buffer transistor having a control terminal coupled to a first output of the latch; a first write transistor having a conduction terminal coupled to the first output of the latch and a control terminal coupled to a first write bitline; and a second write transistor having a conduction terminal coupled to a second output of the latch and a control terminal coupled to a second write bitline, wherein the latch circuit includes:
a first inverter having an input coupled to the first output of the latch and an output coupled to the second output of the latch; anda second inverter having an input coupled to the second output of the latch and an output coupled to the first output of the latch, wherein the first inverter includes an enable transistor, wherein a control terminal of the enable transistor is coupled to the first write bitline, and wherein the enable transistor is configured to prevent the first inverter from increasing a voltage value of the second output of the latch when the enable transistor is off.