Use of error correcting code to carry additional data bits

摘要

Integrated circuits, systems and methods are disclosed in which data bits protected by error correction code (ECC) detection and correction may be increased such that a combination of primary and additional bits may also be ECC protected using existing ECC allocation, without affecting ECC capabilities. For example, the additional bits may be encoded into phantom bits that are in turn used in combination with the primary bits, to generate an ECC. This ECC may then be combined with the primary bits to form a code word. The code word may be transmitted (or stored) so that when the data bits are received (or retrieved), assumed values of the phantom bits may be decoded, using the ECC, back into the additional bits without the phantom bits or the additional bits ever having transmitted (or stored).

主权项

1. An integrated circuit comprising:
a data encoding circuit to prepare data for error correction, the data encoding circuit further to:
receive a plurality of first data bits;receive a plurality of second data bits; andgenerate an error correcting code (ECC) from a combination of the plurality of first data bits and a plurality of third data bits derived from a conversion of the plurality of second data bits, processing logic to form a code word from a combination of the ECC and the plurality of first data bits; wherein a first combination of the plurality of second data bits enables correction of single bit errors and detection of double bit errors in the code word, and wherein a plurality of other combinations of the plurality of second data bits enables detection of single bit errors in the code word.