SRAM multi-cell operations

摘要

A multi-memory cell operator includes a non-destructive memory array, an activation unit and a multiple column decoder. The non-destructive memory array has first and second bit lines per column. The activation unit activates at least two cells in a column of the memory array at the same time thereby to generate multiple Boolean function outputs of the data and of complementary data of the at least two cells on the first bit line and different multiple Boolean function outputs of the data and of the complementary data on the second bit line. The multiple column decoder at least activates the first and second bit lines of multiple selected columns for reading or writing. The multiple column decoder also includes a write unit to write the output of the first bit line, the second bit line or both bit lines of the selected columns into the memory array.

主权项

1. A multi-memory cell operator comprising:
a non-destructive memory array which stores data, said array having first and second bit lines per column; an activation unit to activate at least two cells in a column of said memory array at the same time thereby to generate multiple Boolean function outputs of said data and of complementary data of said at least two cells on said first bit line and different multiple Boolean function outputs of said data and of said complementary data on said second bit line; and a multiple column decoder at least to activate said first and second bit lines of multiple selected columns for reading or writing.