发明名称 System and method for testing fuse blow reliability for integrated circuits
摘要 System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre-charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.
申请公布号 US9557364(B2) 申请公布日期 2017.01.31
申请号 US201414286159 申请日期 2014.05.23
申请人 TESSERA, INC. 发明人 Parris Michael Curtis
分类号 G01R31/02;G01R31/07;G11C29/02 主分类号 G01R31/02
代理机构 代理人
主权项 1. A fuse blow detection circuit, comprising: a fuse circuit comprising a fuse having a first end coupled to ground; a common node coupled to a second end of said fuse; a pre-charge circuit coupled to said common node for pre-charging said common node to a pre-charged HIGH level; an inverter having an inverter output and an inverter input, wherein said inverter input is coupled to said common node; a feedback latch coupled between a voltage source and ground and having a latch input coupled to said inverter output and a latch output coupled to said common node, wherein said feedback latch comprises a p-channel field effect transistor (FET) having a gate coupled to said inverter output, a source coupled to said voltage source, and a drain coupled to said common node, and an n-channel FET having a gate coupled to said inverter output, a source coupled to said common node, and a drain coupled to said ground; and a test circuit coupled to said common node, wherein in a normal mode said test circuit adds strength to said feedback latch for purposes of maintaining said common node at said pre-charged HIGH level, such that in a test mode said feedback latch is weaker than in said normal mode for purposes of maintaining said common node at said pre-charged HIGH level, wherein said test circuit comprises a contribution transistor having a gate coupled to said output and a drain coupled to said common node, and a switch transistor having a source coupled to said voltage source, a drain coupled to said source of said contribution transistor and a gate controlled by a test mode signal, wherein said p-channel FET has a width/length ratio that is greater than or equal to 1.8 times the wide the length ratio of the p-channel FET.
地址 San Jose CA US