Semiconductor device

摘要

The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line). The decode circuit includes a level shifter to step up a signal after predecode. The selection signal is generated by decoding predecode signals which are stepped up by the level shifter in the logical operation circuit. A logic gate to invert the logical level of the predecode signal depending on an operation mode is provided in the preceding stage of each level shifter. When decoding the stepped-up predecode signal, the logical operation circuit performs a different logical operation depending on the operation mode.

主权项

1. A semiconductor device comprising:
a memory array provided with electrically rewritable nonvolatile memory cells arranged in a matrix; a driver circuit operable to drive a plurality of word lines each corresponding to a row of the memory array; and a decode circuit operable to generate a plurality of selection signals to select each of the word lines based on a plurality of predecode signals, and operable to supply the generated selection signals to the driver circuit, wherein the decode circuit comprises: a plurality of first logic gates each operable to invert a logical level of the corresponding predecode signal according to an operation mode; a plurality of first level shifters each operable to convert one of the corresponding predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and a plurality of first logic circuits operable to generate the selection signal by performing a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the first level shifters, and wherein each of the first logic circuits performs a different logical operation according to the operation mode, wherein the memory array is divided into a plurality of blocks every plurality of rows of the memory array, wherein the driver circuit comprises: a plurality of driver groups respectively corresponding to the blocks, wherein each of the driver groups comprises: a first power supply line on a low potential side; a second power supply line on a high potential side; and a plurality of drivers operating with a voltage supplied from the first power supply line and the second power supply line, and each operable to drive a memory cell of the corresponding row of the corresponding block, wherein the decode circuit comprises: a first decode circuit operable to supply a first power supply potential to the first power supply line of each of the driver groups; and a second decode circuit operable to supply a second power supply potential to the second power supply line of each of the driver groups, and wherein the first decode circuit comprises: the first logic gates; the first level shifters; and the first logic circuits each operable to supply the first power supply potential to the corresponding first power supply line as the selection signal, wherein the second decode circuit comprises: a plurality of second level shifters each operable to convert the corresponding predecode signal into a step-up signal of a voltage level according to the operation mode; and a plurality of second logic circuits each operable to perform a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the second level shifters to generate the second power supply potential, and operable to supply the generated second power supply potential to the corresponding second power supply line as the selection signal, and wherein each of the second logic circuits performs the same logical operation irrespective of the operation mode.