发明名称 Data driver and display device driving method
摘要 A driving method for driving a display apparatus including a plurality of pixels, a plurality of data lines and a data driver. The data driver includes a first latch outputting a first sample data signal to a second latch, the second latch, a first charge sharing line and a second charge sharing line. The method includes performing a first charge sharing when a polarity of one of the pixels changes so as to output a first calibrated data signal to the data line electrically coupled to the pixel, and executing a second charge sharing when the most significant bit of the first sample data signal is different from the most significant bit of the second sample data signal so as to output a second adjusted data signal to the data line.
申请公布号 US9558698(B2) 申请公布日期 2017.01.31
申请号 US201414566672 申请日期 2014.12.10
申请人 AU OPTRONICS CORP. 发明人 Chen Wei-Jyun;Chung Chun-Fan;Yeh Szu-Che
分类号 G09G3/36 主分类号 G09G3/36
代理机构 WPAT, PC 代理人 WPAT, PC ;King Justin
主权项 1. An electric charge share device, electrically connected to a data driver and a data line, comprising: a data detection unit configured to determine if a most-significant-bit of a first sample data signal from the data driver is identical to a most-significant-bit of a second sample data signal from the data driver; a first charge share line; a second charge share line; and a data signal charge share unit configured to receive a data signal from the data driver, electrically connected to the data detection unit, the first charge share line and the second charge share line, and comprising: a first switch comprising: a first terminal coupled to the first charge share line;a second terminal coupled to the data line; anda control terminal;a second switch comprising: a first terminal coupled to the second charge share line;a second terminal coupled to the data line; anda control terminal;a first logic unit, coupled to the control terminal of the first switch; configured to control if the first switch is turned on according to whether a polarity of the data line changes, the polarity of the data line, and whether a difference between the first sample data signal and the second sample data signal is larger than a predetermined value; and comprising: a first OR-gate, comprising: a first input terminal configured to receive a polarity switch signal so as to be informed whether the polarity of the data line changes;a second input terminal; andan output terminal coupled to the control terminal of the first switch; anda first AND-gate, comprising: a first input terminal coupled to the data detection unit;a second input terminal coupled to the polarity comparator; andan output terminal coupled to the second input terminal of the first OR-gate;a second logic unit, coupled to the control terminal of the second switch; configured to control if the second switch is turned on according to whether the polarity of the data line changes, the polarity of the data line, and whether the difference between the first sample data signal and the second sample data signal is larger than the predetermined value; and comprising: a second OR-gate, comprising: a first input terminal configured to receive the polarity switch signal so as to be informed whether the polarity of the data line changes;a second input terminal; andan output terminal coupled to the control terminal of the second switch;a second AND-gate, comprising: a first input terminal coupled to the data detection unit;a second input terminal; andan output terminal coupled to the second input terminal of the second OR-gate; andan inverter, comprising: an input terminal coupled to the polarity comparator; andan output terminal coupled to the second input terminal of the second AND-gate; anda polarity comparator, configured to compare the data signal with a voltage value with a predetermined voltage level so as to determine the polarity of the data line and the pixel coupled to the data line, comprising: a first terminal coupled to the data line;a second terminal coupled to the predetermined voltage level; andan output terminal coupled to the first logic unit and the second logic unit; wherein when the most-significant-bit of the first sample data signal is not identical to the most-significant-bit of the second sample data signal, the data line is selectively coupled to the first charge share line or the second charge share line according to a polarity of a common voltage signal of a pixel connected to the data line.
地址 Hsin-Chu TW