Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit

摘要

A circuit for generating clock signals enabling the latching of data is described. The circuit comprises a pulse generator coupled to receive an input clock signal at an input and to generate an output clock signal at an output; a latch circuit coupled to receive the output clock signal; and a pulse shaping circuit coupled to receive a feedback signal; wherein a pulse width of the output clock signal is determined by the feedback signal and the input signal coupled to the pulse generator. A method of generating clock signals enabling the latching of data is also described.

主权项

1. A circuit for generating clock signals enabling the latching of data, the circuit comprising:
a pulse generator coupled to receive an input clock signal at an input and to generate an output clock signal at an output; a plurality of latch circuits coupled to receive the output clock signal; and a pulse shaping circuit coupled to receive a feedback signal from a latch circuit of the plurality of latch circuits that is furthest for the output clock signal to travel from the pulse generator; wherein a pulse width of the output clock signal is determined by the feedback signal and the input clock signal coupled to the pulse generator.