发明名称 Packet shaping in a network processor
摘要 A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.
申请公布号 US9559982(B2) 申请公布日期 2017.01.31
申请号 US201414194038 申请日期 2014.02.28
申请人 Cavium, Inc. 发明人 Folsom Brian Robert;Tompkins Joseph B.;Snyder, II Wilson P.;Kessler Richard E.;Langevin Edwin;Jones Andrew J.;Robbins Ethan F.
分类号 H04L12/28;H04L12/56;H04L12/911;H04L12/721;H04L12/741;H04L29/06;G06F13/42;H04L12/861 主分类号 H04L12/28
代理机构 Hamilton, Brook, Smith & Reynolds, P.C. 代理人 Hamilton, Brook, Smith & Reynolds, P.C.
主权项 1. A circuit for managing transmittal of packets, the circuit comprising: a packet descriptor manager (PDM) circuit module configured to generate a metapacket from a command signal, the metapacket indicating a size and a destination of a packet to be transmitted by the circuit, the metapacket including an entry stating the size of the packet; a packet scheduling engine (PSE) circuit module configured to compare a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, the PSE determining an order in which to transmit the packet among a plurality of packets based on the comparison; and a packet engines and buffering (PEB) circuit module configured to process the packet and cause a processed packet to be transmitted toward the destination according to the order determined by the PSE; wherein the PSE is further configured to compare, for a plurality of nodes in a path between the circuit and the destination, a packet transmission rate associated with the node against at least one of a peak rate and a committed rate associated with the node, the PSE determining the order based on the comparisons.
地址 San Jose CA US