发明名称 Reconfigurable processor for parallel processing and operation method of the reconfigurable processor
摘要 A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instruction word (VLIW) logic and a coarse grained architecture (CGA) logic to be used based on the stored status value; a VLIW register configured to store processed data according to the VLIW logic; and a CGA register configured to store processed data according to the CGA logic.
申请公布号 US9558003(B2) 申请公布日期 2017.01.31
申请号 US201314092060 申请日期 2013.11.27
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Kim Doo Hyun;Song Joon Ho;Kim Do Hyung;Lee Shi Hwa
分类号 G06F9/38;G06F9/30;G06F15/78 主分类号 G06F9/38
代理机构 Staas & Halsey LLP 代理人 Staas & Halsey LLP
主权项 1. A reconfigurable processor, comprising: a status register configured to store a status value; a control register configured to store pending information used to adjust a point in time for initiating a subsequent program by verifying whether an operation according to coarse grained architecture (CGA) logic is terminated; a parallel processing scheduler configured to determine whether to execute very long instruction word (VLIW) logic and the CGA logic in a single execution mode or in a parallel mode based on the stored status value and pending information, and to schedule at least one of the VLIW logic and the CGA logic to be executed based on the determination; a VLIW register configured to store VLIW processed data according to the VLIW logic; and a CGA register configured to store CGA processed data according to the CGA logic, wherein the parallel processing scheduler is configured to: schedule processed data to be duplicated between the VLIW register and the CGA register in response to execution of each of the VLIW logic and the CGA logic, when the processor is operated in the single execution mode, andschedule processed data to be duplicated between the VLIW register and the CGA register after synchronizing of a termination point in time between the VLIW logic and the CGA logic, when the processor is operated in the parallel mode.
地址 Suwon-si KR