Transceiver system with reduced latency uncertainty

摘要

A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

主权项

1. A transceiver system comprising:
a word aligner, wherein each word of a plurality of words aligned by the word aligner has a plurality of bits and the word aligner aligns the plurality of words to a word boundary; and a bit slipper coupled to the word aligner; wherein the bit slipper receives information regarding word alignment from the word aligner, further wherein the bit slipper slips bits in such a way so that total delay due to word alignment by the word aligner and bit slipping by the bit slipper is constant for all phases of a recovered clock signal.