| 主权项 |
1. A latch circuit, comprising:
an input stage, for receiving at least a clock signal and a data control signal; an amplifying stage, coupled to the input stage and supplied by a supply voltage and a ground voltage, for outputting a data value according to the clock signal and the data control signal; and a clock gating circuit, coupled to the amplifying stage, for disconnecting a path between the supply voltage and the ground voltage while the clock signal has a state transition; wherein the amplifying stage comprises: a first N-type metal-oxide-semiconductor (NMOS) and a second NMOS, wherein source electrodes of the first NMOS and the second NMOS are coupled to the ground voltage; a first P-type metal-oxide-semiconductor (PMOS) and a second PMOS, wherein source electrodes of the first PMOS and the second PMOS are coupled to the supply voltage; and a differential output terminals comprising a first output terminal and a second output terminal, wherein the first output terminal is electrically connected to gate electrodes of the first NMOS and the first PMOS, and the second output terminal is electrically connected to gate electrodes of the second NMOS and the second PMOS; wherein the clock gating circuit is arranged to selectively connect the first output terminal to drain electrodes of the second NMOS and the second PMOS or not, and to selectively connect the second output terminal to drain electrodes of the first NMOS and the first PMOS or not. |
