Fast process flow, on-wafer interconnection and singulation for MEPV

摘要

A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.

主权项

1. A method comprising:
providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer; depositing a metal interconnect on the first dielectric layer such that the deposited interconnect is electrically connected to at least two of the device cells and lies across a boundary between at least two of the electrically connected device cells; depositing a second dielectric layer over the first dielectric layer and over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer.