| 摘要 |
A device for implementing FFT/DFT is disclosed, comprising: a first multiplier, a second multiplier, a first adder, a second adder, a first multiplexer, a second multiplexer, a first accumulator register, a second accumulator register and a negation controller, wherein the first adder is configured to accumulate the output signals of the first multiplexer, the first multiplier and the second multiplier and input an accumulated signal to the first accumulator register; the second adder is configured to accumulate the output signals of the second multiplexer, the first multiplier and the second multiplier and input an accumulated signal to the second accumulator register; the first accumulator register is configured to output the output signal of the first adder or feed the same back to the first multiplexer; and the second accumulator register is configured to output the output signal of the second adder or feed the same back to the second multiplexer. |
| 主权项 |
1. A device for implementing Fast Fourier Transformation/Discrete Fourier Transformation (FFT/DFT), comprising: a first multiplier, a second multiplier, a first adder, a second adder, a first multiplexer, a second multiplexer, a first accumulator register, a second accumulator register and a negation controller configured to perform negation operation on output signal of the first multiplier and/or the second multiplier, wherein
an input end of the first adder is connected with an output end of the first multiplexer, an output end of the first multiplier and an output end of the second multiplier respectively, an output end of the first adder is connected with an input end of the first accumulator register, and the first adder is configured to accumulate an output signal of the first multiplexer, an output signal of the first multiplier and an output signal of the second multiplier, and input an accumulated signal obtained to the first accumulator register; an input end of the second adder is connected with the output end of the first multiplier, the output end of the second multiplier and an output end of the second multiplexer respectively, an output end of the second adder is connected with an input end of the second accumulator register, and the second adder is configured to accumulate an output signal of the second multiplexer, the output signal of the first multiplier and the output signal of the second multiplier, and input an accumulated signal obtained to the second accumulator register; and the first accumulator register is configured to output an output signal of the first adder or feed the output signal of the first adder back to an input end of the first multiplexer; and the second accumulator register is configured to output an output signal of the second adder or feed the output signal of the second adder back to an input end of the second multiplexer. |
