发明名称 Synchronization method, multi-core processor system, and synchronization system
摘要 A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs.
申请公布号 US9558152(B2) 申请公布日期 2017.01.31
申请号 US201314026469 申请日期 2013.09.13
申请人 FUJITSU LIMITED 发明人 Yamashita Koichiro;Yamauchi Hiromasa;Suzuki Takahisa;Kurihara Koji
分类号 G06F9/46;G06F15/78;G06F9/52;G06F9/54;G06F15/167;G06F9/45;G06F9/38;G06F9/30 主分类号 G06F9/46
代理机构 Staas & Halsey LLP 代理人 Staas & Halsey LLP
主权项 1. A synchronization method executed by a multi-processor system, the synchronization method comprising: sending, by a first CPU among a plurality of CPUs, a synchronous signal that is issued based on a synchronous command included in a synchronization processing to the plurality of CPUs excluding the first CPU, the plurality of CPUs accessing a first shared memory area to execute the synchronization processing; increasing, by a second CPU among the plurality of CPUs and different from the first CPU and based on receiving the synchronous signal from the first CPU, an arrival count for a synchronous point by one, the synchronous point indicating a position of the synchronous command in the synchronization processing and the arrival count indicating a number of CPUs arriving at the synchronous point among the plurality of CPUs; sending, by the second CPU, a ready signal indicating an arrival to the synchronous point, to the plurality of CPUs excluding the first CPU and the second CPU as a result of increasing the arrival count by one; creating, by the second CPU, a second shared memory area and a third shared memory area that are a duplication of the first shared memory area and accessing, by the second CPU, data stored only in the second shared memory area to execute a subsequent processing subsequent to the synchronization processing when the arrival count is not equal to count of the CPUs excluding the first CPU as a result of increasing the arrival count by one; when the arrival count is equal to the count of the CPUs excluding the first CPU as a result of receiving the ready signal from a CPU different from the second CPU and the first CPU: first comparing, by the second CPU, the second shared memory area and the third shared memory area, when a first comparing result indicates a coincidence, second comparing, by the second CPU, the first shared memory area and the second shared memory area,when a second comparing result indicates a coincidence, the CPUs excluding the first CPU are synchronized and the synchronization processing is complete,when the first comparing result or the second comparing result indicates a non-coincidence, interrupting and re-executing the subsequent processing.
地址 Kawasaki JP