Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device

摘要

System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.

主权项

1. A data processing system, comprising:
a data handling device, comprising:
a data requestor endpoint configured for originating first packet requests for transmission on a first packetized memory link to a first memory device; anda data handling endpoint configured for:
interpreting second packet requests received by the data handling endpoint on a second packetized memory link from at least one additional data handling device; andconveying data bidirectionally across the second packetized memory link to and from the at least one additional data handling device in response to the second packet requests;wherein the first packetized memory link and the second packetized memory link are separate but include a same type of link protocol and a same type of physical interface.