| 发明名称 | Memory system including cache | ||
| 摘要 | According to one embodiment, a memory system comprises a first storage device containing a nonvolatile semiconductor memory and a controller configured to control the first storage device. Data from a data processor is written to the first storage device, the data is written to a second storage device. The controller transmits information indicating that data to be read is absent in the first storage device to the data processor when a read error occurs, the read error disables reading of data from the first storage device in response to a read request supplied from the data processor. | ||
| 申请公布号 | US9558065(B2) | 申请公布日期 | 2017.01.31 |
| 申请号 | US201514722848 | 申请日期 | 2015.05.27 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Yoshida Hideki;Kanno Shinichi |
| 分类号 | G11C29/00;G06F11/10;G06F3/06 | 主分类号 | G11C29/00 |
| 代理机构 | White & Case LLP | 代理人 | White & Case LLP |
| 主权项 | 1. A memory system comprising: a first storage device comprising a nonvolatile semiconductor memory; and a controller configured to control the first storage device, wherein data from a data processor is written to the first storage device, the data is written to a second storage device, and the controller transmits information indicating that data to be read is absent in the first storage device to the processor when a read error occurs, the read error disables reading of data from the first storage device in response to a read request supplied from the data processor. | ||
| 地址 | Tokyo JP | ||