FinFET-based ESD devices and methods for forming the same

摘要

A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.

主权项

1. A method of manufacturing a semiconductor device, the method comprising:
forming an isolation region over a substrate between a first fin and a second fin, the isolation region have a first surface facing away from the substrate; forming a first gate stack over the first fin and the second fin, wherein after the forming the first gate stack the first fin comprises a first portion covered by the first gate stack and a second portion that is uncovered by the first gate stack and the second fin comprises a third portion covered by the first gate stack and a fourth portion that is uncovered by the first gate stack; removing the second portion of the first fin to expose a first surface of semiconductor material and removing the fourth portion of the second fin to expose a second surface of semiconductor material; and epitaxially growing a first semiconductor material onto the first surface and epitaxially growing a second semiconductor material onto the second surface, wherein the first semiconductor material merges with the second semiconductor material at a first point that is located a first distance from the first gate stack and does not merge with the second semiconductor material at a second point that is located at a second distance from the first gate stack different from the first distance, wherein the first point and the second point are located a same distance away from the first surface of the isolation region.