Electrophoretic display device

摘要

This specification relates to an electrophoretic display device, and particularly, to an electrophoretic display device capable of reducing power consumption by blocking a leakage current generated from a Power On Reset (POR) circuit which resets each driver Integrated Circuit (IC) at an initial period, whereby a transistor as an active element connected to a POR circuit may be turned on by applying a positive voltage, other than a power supply voltage, to a gate thereof at an image update period to drive a bias block, and thereafter turned off at an image static period, thereby blocking a leakage current and accordingly reducing power consumption.

主权项

1. An electrophoretic display device comprising:
an electrophoretic panel driven by a time division into an image update period and an image static period and having a plurality pixels defined thereon to display the image; a gate driver having at least one gate driver integrated circuit (IC) to apply a gate driving voltage to the plurality of pixels; a data driver having at least one data driver integrated circuit to apply a data voltage to the plurality of pixels; and a power supply unit to generate a gate high voltage, a gate low voltage, a positive voltage, a negative voltage and a ground voltage, wherein at least one of the gate driver integrated circuit and the data driver integrated circuit comprises:
a reset circuit to generate a reset signal in a power-on state, the reset circuit including:
a first node connected to an output end, the output end to supply the reset signal;a second node connected to a bias block;a resistor having one end to which a power supply voltage (VCC) is applied and the other end connected to the first node; anda capacitor having one end connected to the first node and the other end connected to the second node; anda thin film transistor (TFT) synchronized with the positive voltage, the thin film transistor connected between the second node and the ground voltage, the thin film transistor to supply a control signal to the bias block in response to a signal output from the second node of the reset circuit, wherein the capacitor is electrically connected in series between the resistor and the thin film transistor, wherein the output of the positive voltage from the power supply unit to the data driver or the gate driver is stopped at a time point when the image static period starts such that the positive voltage is not supplied to the gate of the thin film transistor.