Method of forming stacked trench contacts and structures formed thereby

摘要

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

主权项

1. A semiconductor structure, comprising:
a gate electrode above at least a portion of a silicon substrate; a first source/drain region in the semiconductor substrate, on a first side of the gate electrode; a second source/drain region in the semiconductor substrate, on a second side of the gate electrode opposite the first side; a first dielectric sidewall spacer adjacent to the first side of the gate electrode; a second dielectric sidewall spacer adjacent to the second side of the gate electrode; a nitride dielectric layer laterally adjacent the first and second dielectric sidewall spacers, wherein the nitride dielectric layer, the first and second dielectric sidewall spacers, and the gate electrode each have an uppermost surface that is substantially co-planar; an interlayer dielectric layer laterally adjacent the nitride dielectric layer; a gate dielectric cap layer on the nitride dielectric layer, on the first and second dielectric sidewall spacers, on the gate electrode, and over a portion of the interlayer dielectric layer; a conductive contact structure adjacent the interlayer dielectric layer, laterally adjacent the gate electrode stack and in contact with one of the pair of source/drain regions, the conductive contact structure having substantially vertical sidewalls; and a conductive via structure over and in contact with the conductive contact structure, the conductive via structure having an upper portion wider than a lower portion, wherein the conductive contact structure is wider than the conductive via structure at a location where the conductive contact structure and the conductive via structure meet, and wherein the location is below an uppermost surface of the gate dielectric cap layer.