| 摘要 |
A capacitance detecting method disclosed herein, which achieves a good detection accuracy, a good resolution, and a high-speed operation, (A) (a) drives, on the basis of code sequences (di (=di1, di2, . . . , diN, where i=1, . . . , M)) which are orthogonal to one another and include ±1 and each of which has a length N, drive lines (DL1 through DLM) in parallel for each of (I) a first capacitance column (Ci1) between the drive lines and a first sense line (SL1) and (II) a second capacitance column (Ci2) between the drive lines and a second sense line (SL2) so that voltages ±V are applied and (b) outputs outputs (sFirst=(s11, s12, . . . , s1N)) from the first capacitance column (Ci1) and outputs (sSecond=(s21, s22, . . . , s2N)) from the second capacitance column (Ci2), and (B) estimates (a) on the basis of a first inner product operation of the outputs (sFirst) and the code sequences (di), a first capacitance value in the first capacitance column (Ci1) and (b) on the basis of a second inner product operation of the outputs (sSecond) and the code sequences (di), a second capacitance value in the second capacitance column (Ci2). |
| 主权项 |
1. A capacitance detecting method, comprising the steps of:
(A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , and where M<N) each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the step (A) driving, when the analog integrator is reset, the M drive lines at a first voltage represented by a voltage Vref and driving, when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the M drive lines at (i) a second voltage for an element of +1 in the code sequences, the second voltage being represented by a voltage (Vref+V), and (ii) a third voltage for an element of −1 in the code sequences, the third voltage being represented by a voltage (Vref−V). |
