Operating a Pipeline Flattener in Order to Track Instructions for Complex Breakpoints

摘要

A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

主权项

1. A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener, the processor comprising a pipeline having a plurality of pipeline stages and a plurality of pipeline registers which are coupled between the pipeline stages, wherein the pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages and wherein the pipeline flattener is configured to set the trigger register of the pipeline stage receiving an instruction to a predetermined trigger value indicating that the received instruction is selected for debug tracking, forward the trigger through the trigger registers of the pipeline together with the received instruction, determine whether the trigger indicates that the assigned instruction is selected for debug tracking and if so, provide the tracked debug data to a debug unit of the semiconductor device.