MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

摘要

A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers.

主权项

1. A memory device, comprising:
a semiconductor substrate; a dielectric isolation layer, disposed on the semiconductor substrate; a first conductive layer, disposed on the isolation layer; a contact plug, passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer; a plurality insulating layers, disposed on the first conductive layer; a plurality of second conductive layers, alternatively stacked the insulating layers and insulated from the first conductive layer; a channel layer, disposed on at least one sidewall of at least one first through opening and electrically contact to the contact plug, wherein the first through opening passes through the insulating layers the second conductive layers, so as to expose the contact plug; and a memory layer, disposed between the channel layer and the second conductive layers, wherein the memory layer comprises: a tunnel oxide layer, disposed between the channel layer and the second conductor layers; a plurality of floating gate electrodes, respectively disposed between each of the second conductor layers and the tunnel oxide layer; and a plurality of spacing layers, respectively disposed between each of the second conductor layers and the corresponding one of the floating gate electrodes.