MULTI-DIE PACKAGE STRUCTURES

摘要

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

主权项

1. A device comprising:
a packaging substrate having a surface wherein the surface has a recess formed therein; a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface; a spacer layer disposed on the surface of the first integrated circuit die wherein the spacer layer has a first surface proximate to the first integrated circuit die and a second surface opposite to the first surface; a dielectric layer disposed on the surface of the coreless packaging substrate and on the second surface of the spacer layer; and a second integrated circuit die disposed on the dielectric layer.