发明名称 |
ADDRESS TRANSLATION AND DATA PRE-FETCH IN A CACHE MEMORY SYSTEM |
摘要 |
Systems, methods, and computer program products are disclosed for reducing latency in a system that includes one or more processing devices, a system memory, and a cache memory. A pre-fetch command that identifies requested data is received from a requestor device. The requested data is pre-fetched from the system memory into the cache memory in response to the pre-fetch command. The data pre-fetch may be preceded by a pre-fetch of an address translation. A data access request corresponding to the pre-fetch command is then received, and in response to the data access request the data is provided from the cache memory to the requestor device. |
申请公布号 |
WO2017014914(A1) |
申请公布日期 |
2017.01.26 |
申请号 |
WO2016US39456 |
申请日期 |
2016.06.26 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
ZGHAL, Tarek;ARTIERI, Alain Dominique;PODAIMA, Jason Edward;VARIA, Meghal;GADELRAB, Serag |
分类号 |
G06F12/0862 |
主分类号 |
G06F12/0862 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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