发明名称 Buried Channel Deeply Depleted Channel Transistor
摘要 Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
申请公布号 US2017025457(A1) 申请公布日期 2017.01.26
申请号 US201615285308 申请日期 2016.10.04
申请人 Mie Fujitsu Semiconductor Limited 发明人 Bakhishev Teymur;Wang Lingquan;Zhao Dalong;Ranade Pushkar;Thompson Scott E.
分类号 H01L27/146 主分类号 H01L27/146
代理机构 代理人
主权项 1. A semiconductor device, comprising: a semiconductor substrate having at least one device region of a first conductivity type; a source region and a drain region of a second conductivity type formed in the at least one device region and separated by a channel length; a channel region of the second conductivity type formed in the at least one device region between the source region and the drain region; and a screening region of the first conductivity type formed in the at least one device region below the channel region and between the source region and the drain region, an effective doping density of the screening region being substantially higher than an effective doping density of the at least one device region; and a gate structure formed on the at least one device region above the channel region, wherein the channel region is modified, in response to a bias voltage at the gate structure, to provide a surface depletion layer below the gate structure, a buried depletion layer at an interface of the channel region and the screening region, and a buried channel layer between the surface depletion region and the buried depletion region electrically coupling the source region and the drain region, and wherein the buried depletion layer is substantially located in channel region.
地址 Kuwana JP