Orthogonal Differential Vector Signaling Codes with Embedded Clock

摘要

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

主权项

1. A method comprising:
receiving, at a plurality of multi-input comparators (MICs) via a multi-wire bus, a set of symbols of a codeword of a vector signaling code, the set of symbols representing a transformation of an input vector with a non-simple orthogonal or unitary matrix, the input vector comprising a plurality of sub-channels, wherein at least one sub-channel corresponds to an input data signal and wherein at least one sub-channel corresponds to a data-aligned strobe signal; forming a plurality of data MIC output signals, each data MIC output signal of the plurality of data MIC output signals generated by a corresponding MIC comparing a subset of symbols of the codeword, and wherein each data MIC has a set of respective data input coefficients corresponding to a respective subchannel; generating a timing MIC output signal generated by a timing MIC comparing a respective subset of symbols of the codeword, said respective subset including at least one symbol in common with each subset of symbols utilized by a data MIC forming a data MIC output signal, wherein the timing MIC has a set of timing input coefficients orthogonal to each set of respective data input coefficients to remove the at least one input data signal from the timing MIC output signal; and, sampling the plurality of data MIC output signals according to the timing MIC output signal.