| 摘要 |
A gate driver on array circuit unit (100, 200), comprising: a gate driver on array register module (110) with a shift register unit and a gate driver on array output module (120) with a digital logic circuit. A current-level exciting pulse, a second additional clock signal, a first clock signal and a second clock signal are provided for the digital logic circuit, so that only in a first half pulse width period of the current-level exciting pulse, a first gate line drive pulse corresponding to a first half period of the first clock signal is output at a first current-level output end, and a second gate line drive pulse corresponding to a second half period of the second clock signal is output at a second current-level output end. Also disclosed are a gate driver on array circuit formed by cascading the gate driver on array circuit units (100, 200), and a display panel comprising the drive circuit. The single GOA unit can output a gate drive pulse for two rows of pixels, so that the number of GOA circuit units required is reduced. |
