| 发明名称 |
ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING |
| 摘要 |
A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs. |
| 申请公布号 |
US2017023647(A1) |
申请公布日期 |
2017.01.26 |
| 申请号 |
US201615284070 |
申请日期 |
2016.10.03 |
| 申请人 |
STMicroelectronics International N.V. |
发明人 |
Syed Danish Hasan |
| 分类号 |
G01R31/317;G01R31/3177 |
主分类号 |
G01R31/317 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A system, comprising:
an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern; an OCC test circuit coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs; a test output logic circuit configured to receive the OCC test outputs from the OCC test circuit; and a debug controller operable to configure the test output logic circuit to output the OCC test outputs. |
| 地址 |
Amsterdam NL |
