INTERDIGITIZED POLYSYMMETRIC FANOUTS, AND ASSOCIATED SYSTEMS AND METHODS

摘要

Systems and methods for testing semiconductor wafers using a wafer translator are disclosed herein. In one embodiment, an apparatus for testing semiconductor dies includes a wafer translator having a wafer-side facing the dies and an inquiry-side facing away from the wafer-side. The inquiry-side of the wafer translator carries a first and a second plurality of inquiry-side contact structures. The first plurality of the inquiry-side contact structures is interleaved with the second plurality of the inquiry-side contact structures.

主权项

1. An apparatus for testing semiconductor dies, comprising:
a wafer translator having
a wafer-side facing the dies, wherein the wafer-side of the wafer translator carries a first and a second plurality of wafer-side contact structures, wherein the first plurality of the wafer-side contact structures is configured to face die contacts of a first die, and wherein the second plurality of the wafer-side contact structures is configured to face the die contacts of a second die;an inquiry-side facing away from the wafer-side, wherein the inquiry-side of the wafer translator carries a first and a second plurality of inquiry-side contact structures; andconductive traces connecting the first plurality of the wafer-side contact structures with the first plurality of inquiry-side contact structures, and the second plurality of the wafer-side contact structures with the second plurality of inquiry-side contact structures, wherein the first plurality of the inquiry-side contact structures is interleaved with the second plurality of the inquiry-side contact structures.