发明名称 |
Highly Efficient Method For Inverse Multiplexing In An Ethernet Access Network |
摘要 |
An Ethernet access network system for inverse multiplexing can comprise a reconciliation sublayer (RS) transmitter and an RS receiver. The RS transmitter can be configured to retrieve an LLID from a data stream; determine bonded channel connections at an ONU corresponding to the LLID, wherein each bonded channel connection is coupled to a FIFO buffer of a plurality of FIFO buffers; route one or more packets of the data stream to a first FIFO buffer of the plurality of FIFO buffers in response to the first FIFO buffer having a lowest fill rate; and transmit the one or more packets across the bonded channel connections. The RS receiver can be configured to receive the one or more packets; and arrange the one or more packets in order based on a packet order indicator. |
申请公布号 |
US2017026128(A1) |
申请公布日期 |
2017.01.26 |
申请号 |
US201615215088 |
申请日期 |
2016.07.20 |
申请人 |
Futurewei Technologies, Inc. |
发明人 |
Remein Duane;Effenberger Frank;Luo Yuanqiu |
分类号 |
H04B10/27;H04L12/861;H04L12/741;H04L29/06 |
主分类号 |
H04B10/27 |
代理机构 |
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代理人 |
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主权项 |
1. A reconciliation sublayer (RS) transmitter, comprising:
a Preamble Replacement & Idle Insertion (PRII) component configured to receive a data stream of packets; a multiplexer coupled to the PRII component and configured to selectively route the data stream of packets; a plurality of first-in first-out (FIFO) buffers coupled to the multiplexer and configured to buffer the data stream of packets; and a channel select logic component coupled to the PRII component, the multiplexer, and the plurality of FIFO buffers, wherein the channel select logic component is configured to:
receive Logical Link Identification (LLID) from the data stream, where the LLID identifies an intended endpoint destination for the data stream;retrieve one or more identifiers of buffers corresponding to the LLID from a look-up table;compare fill rates of the plurality of FIFO buffers corresponding to the one or more identifiers of buffers;select a selected buffer having a lowest fill rate of the plurality of FIFO buffers; androute the data stream to the selected buffer in response to a channel select signal provided to the multiplexer by the channel select logic component. |
地址 |
Plano TX US |