DELIVERING INTERRUPTS THROUGH NON-TRANSPARENT BRIDGES IN A PCI-EXPRESS NETWORK

摘要

An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

主权项

1. A management CPU in a PCI Express (PCIe) network, comprising:
a memory; a processor for managing initialization of a plurality of I/O devices coupled to a PCIe fabric of the management CPU, wherein the PCIe fabric includes a non-transparent bridge (NTB) through which the PCIe fabric is coupled to a worker CPU of the PCIe network; the processor being configured to perform operations of: receiving a request from the worker CPU to enable a first I/O device in the PCIe fabric of the management CPU to send a first interrupt to the worker CPU, wherein the worker CPU has assigned a target interrupt register address for receiving the first interrupt; mapping the target interrupt register address to a mapped interrupt register address for use by the first I/O device in the PCIe fabric of the management CPU to sent the first interrupt to the worker CPU through the NTB; and sending an instruction to the first I/O device to register the mapped interrupt register address for the first interrupt in a I/O interrupt vector table of the first I/O device.