发明名称 Shared cache memory control
摘要 A data processing system 2 includes a cache hierarchy having a plurality of local cache memories and a shared cache memory 18. State data 30, 32 stored within the shared cache memory 18 on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.
申请公布号 GB2493592(B) 申请公布日期 2017.01.25
申请号 GB20120010115 申请日期 2012.06.08
申请人 ARM Limited 发明人 Jamshed Jalal;Mark David Werkheiser;Brett Stanley Feero;Michael Alan Filippo
分类号 G06F12/084;G06F12/0811 主分类号 G06F12/084
代理机构 代理人
主权项
地址