发明名称 演算回路、演算処理装置、及び除算方法
摘要 An arithmetic circuit for performing division based on restoring division includes an intermediate remainder register configured to store an intermediate remainder, a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result, a fixed-value multiplication circuit configured to output one or more N-th (N: integer) multiples of the divisor selected in response to the prediction result, one or more subtracters configured to subtract, from the intermediate remainder, the one or more N-th multiples of the divisor output from the fixed-value multiplication circuit, and a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters.
申请公布号 JP6064435(B2) 申请公布日期 2017.01.25
申请号 JP20120182344 申请日期 2012.08.21
申请人 富士通株式会社 发明人 篠宮 研介;北村 健一
分类号 G06F7/535 主分类号 G06F7/535
代理机构 代理人
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