发明名称 薄膜トランジスタおよびその製造方法
摘要 Provided is a back-channel etch type thin-film transistor (TFT) without an etch stopper layer, wherein an oxide semiconductor of the TFT has excellent resistance to an acid etchant and stress stability. The oxide semiconductor layer is a laminate having a first layer comprising tin, indium, and gallium or zinc, and oxygen, and a second layer comprising one or more elements selected from a group consisting indium, zinc, tin and gallium; and oxygen. The TFT is formed, in the following order, a gate insulator film, the second semiconductor layer and the first semiconductor layer; and having a value in a cross section in the lamination direction of the TFT, as determined by [100×(the first layer thickness of directly below a source-drain electrode end−a center portion thickness of the first layer)/the first layer thickness of directly below the source-drain electrode end], of not more than 5%.
申请公布号 JP6068327(B2) 申请公布日期 2017.01.25
申请号 JP20130272886 申请日期 2013.12.27
申请人 株式会社神戸製鋼所 发明人 森田 晋也;越智 元隆;後藤 裕史;釘宮 敏洋;廣瀬 研太
分类号 H01L29/786;H01L21/28;H01L21/306;H01L21/336;H01L21/363;H01L29/417 主分类号 H01L29/786
代理机构 代理人
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