Resistance change memory

摘要

A first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.

主权项

1. A resistance change memory comprising:
a first memory cell array arranged with memory cells having resistance change elements, wherein first ends of the memory cells are connected to first normal bit lines, and second ends of the memory cells are connected to first normal source lines; a first column switch configured to select one of the first normal bit lines, and to connect the selected one of the first normal bit lines to a first global bit line; a second column switch configured to select one of the first normal source lines, and to connect the selected one of the first normal source lines to a first global source line; at least a first reference cell arranged in the first memory cell array, wherein a first end of the first reference cell is connected to a reference bit line and a second end of the first reference cell is connected to a reference source line; a third column switch configured to connect the reference bit line connected to the first reference cell to a second global bit line; a fourth column switch configured to connect the reference source line connected to the first reference cell to the first global source line; a first sense amplifier connected to the first global bit line and the second global bit line, and configured to read data stored in any one of the memory cells; a word line connected to the memory cells, wherein if a read operation is performed, the word line is activated so that at least one of the memory cells is selected; a second memory cell array arranged with memory cells having resistance change elements, wherein first ends of the memory cells are connected to second normal bit lines, and second ends of the memory cells are connected to second normal source lines; a fifth column switch configured to select one of the second normal bit lines, and to connect the selected one of the second normal bit lines to a third global bit line; a sixth column switch configured to select one of the second normal source lines, and to connect the selected one of the second normal source lines to a second global source line; at least a second reference cell arranged in the second memory cell array, wherein a first end of the second reference cell is connected to a second reference bit line and a second end of the second reference cell is connected to a second reference source line; a seventh column switch configured to connect the second reference bit line connected to the second reference cell to a fourth global bit line; an eighth column switch configured to connect the second reference source line connected to the second reference cell to the second global source line; a second sense amplifier, connected to the third global bit line and the fourth global bit line, and configured to read data stored in any one of the memory cells in the second memory cell array; and a switch circuit provided between the second global bit line and the fourth global bit line, and configured to connect the second global bit line and the fourth global bit line, wherein if power is turned on, the first sense amplifier writes first data to the first reference cell, and the second sense amplifier writes second data to the second reference cell.