发明名称 |
Method and apparatus for flip chip packaging co-design and co-designed flip chip package |
摘要 |
The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result. |
申请公布号 |
US9552452(B2) |
申请公布日期 |
2017.01.24 |
申请号 |
US201615088109 |
申请日期 |
2016.03.31 |
申请人 |
MEDIATEK INC. |
发明人 |
Fang Jia-Wei;Huang Shen-Yu |
分类号 |
G06F17/50;H01L23/00 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
Hsu Winston;Margo Scott |
主权项 |
1. A method for flip chip packaging co-design, the method comprising steps of:
providing an Input/Output (I/O) pad information of a chip and a connection information of a PCB; performing an I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a redistribution layer (RDL) routing analysis device to perform a bump pad pitch analysis for the I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and adjusting the I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result. |
地址 |
Hsin-Chu TW |