Crystal-less jitter attenuator

摘要

An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.

主权项

1. An integrated circuit to remove jitter from a clock signal, comprising:
an integrated circuit die, further comprising:
a signal comparator, the signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal, wherein the signal comparator is a frequency comparator that counts a first number of clock cycles occurring on the correction signal within a fixed time window, and the frequency comparator counts a second number of clock cycles occurring on the jittery input clock signal within the fixed window of time;a digital low pass filter, the digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal;a free running crystal-less oscillator, the free running crystal-less oscillator produces a reference signal; anda fractional output divider, the fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter, the fractional output divider utilizes the filtered output signal to establish a value to divide a frequency of the reference signal by to obtain a clean output clock signal, the clean output clock signal is fed back to the signal comparator as the correction signal.