Compact C-multiplier

摘要

The compact C-multiplier includes four MOSFETs operating in the subthreshold region using the translinear principle. The multiplier is controllable to meet designer requirements. A Tanner Tspice simulator is used to confirm the functionality of the design in 0.13 pm CMOS Technology. The circuit operates from a ±0.75 supply voltage. Simulation results indicate that the multiplication factor is large compared to existing designs.

主权项

1. A compact C-multiplier, comprising:
first M1, second M2, third M3 and fourth M4 MOSFETs connected together to form a translinear loop circuit, the translinear loop circuit, the MOSFETs having bias circuits constraining operation of the MOSFETs to a weak inversion mode; and a capacitor C connected to the translinear loop circuit to form a capacitive impedance Zeq; wherein the capacitive impedance Zeq is characterized by the relation:Zeq=1sC⁢1(G+1),where 1/sC is the value of the capacitor in Laplace transform format, and G is gain defined by current ratios of the translinear loop circuit.