PLL circuit and control method thereof

摘要

According to one embodiment, a PLL circuit includes: a phase comparator (13); a pulse width control unit that adjusts a pulse width of comparison results (UP, DN) of the phase comparator (13) and outputs comparison results (UPi, DNi) having a pulse width smaller than that of comparison results (UPp, DNp); a charge pump (14) that outputs a current (Ip) according to the comparison results (UPp, DNp); a charge pump (15) that outputs a current (Ii) according to the comparison results (UPi, DNi); a filter (16) that removes a high-frequency component of a voltage generated based on the current (Ip) and outputs a control voltage (Vp); a filter (17) that outputs, as a control voltage (Vi), a result obtained by integrating the current (Ii); and a voltage control oscillator (18) that generates an oscillating signal having a frequency according to the control voltage (Vp, Vi).

主权项

1. A phase locked loop (PLL) circuit comprising:
a phase comparator that compares a phase of a reference signal with a phase of a feedback signal and outputs a reference comparison result; a pulse width control unit that adjusts a pulse width of the reference comparison result, and outputs a first comparison result and a second comparison result having a pulse width smaller than that of the first comparison result; a first charge pump that outputs a first current according to the first comparison result; a second charge pump that outputs a second current according to the second comparison result; a first filter that removes a high-frequency component of a voltage generated based on the first current, and outputs a first control voltage; a second filter that outputs, as a second control voltage, a result obtained by integrating the second current; and an oscillator that generates an oscillating signal having a frequency according to the first and second control voltages, and feeds the oscillating signal back to the phase comparator as the feedback signal.