Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs

摘要

Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

主权项

1. A semiconductor structure comprising:
a substrate, at least one first semiconductor fin located in a first device region of the substrate, at least one second semiconductor fin located in a second device region of the substrate, at least one third semiconductor fin located in a third device region of the substrate, and at least one fourth semiconductor fin located in a fourth device region of the substrate; a gate cavity which exposes a channel portion of each of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor fin, and the at least one fourth semiconductor fin, wherein the gate cavity is laterally surrounded by an interlevel dielectric (ILD) layer; and a gate stack straddling over the channel portion of each of the at least one first semiconductor fin, the at least one second semiconductor fin, the at least one third semiconductor, and the at least one fourth semiconductor fin, the gate stack comprising: a first gate stack portion straddling over the channel portion of the first semiconductor fin and comprising: a first portion of a gate dielectric located in the first device region directly on the channel portion of the at least one first semiconductor fin, a gate dielectric cap present directly on the first portion of the gate dielectric, a first portion of a p-type work function metal present directly on the gate dielectric cap, a first portion of a barrier layer portion present directly on the first portion of the p-type work functional metal, and a first portion of an n-type work function metal present directly on the first portion of the barrier layer portion; a second gate stack portion straddling over the channel portion of the second semiconductor fin and comprising: a second portion of the gate dielectric located in the second device region directly on the channel portion of the second semiconductor fin, a second portion of the p-type work function metal present directly on the second portion of the gate dielectric, a second portion of the barrier layer portion present directly on the second portion of the p-type work functional metal, a second portion of the n-type work function metal present directly on the second portion of the barrier layer portion, and a first portion of a gate electrode present directly on the second portion of the n-type work function metal; a third gate stack portion straddling over the channel portion of the third semiconductor fin and comprising: a third portion of the gate dielectric located in the third device region directly on the channel portion of the third semiconductor fin, a third portion of the barrier layer portion present directly on the third portion of the gate dielectric, a third portion of the n-type work function metal present directly on the third portion of the barrier layer portion, a metal cap present directly on the third portion of the n-type work function metal, and a second portion of the gate electrode present directly on the metal cap; and a fourth gate stack portion straddling over the channel portion of the fourth semiconductor fin and comprising: a fourth portion of the gate dielectric located in the third device region directly on the channel portion of the third semiconductor fin, a fourth portion of the barrier layer portion present directly on the fourth portion of the gate dielectric, a fourth portion of the n-type work function metal present directly on the fourth portion of the barrier layer portion, and a third portion of the gate electrode present directly on the fourth portion of the n-type work function metal.