Skew detection and correction in time-interleaved analog-to-digital converters

摘要

The present disclosure provides a system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels. A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel, and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel, and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel.

主权项

1. A method for correcting clock skew in a time-interleaved analog-to-digital converter (TIADC), comprising:
receiving at least first and second clock signals along first and second channels, respectively; accounting for a delay of the first channel by applying at least one first adjustment factor to the first and second channels until an edge of the first clock signal is aligned with a transition point of a reference signal; swapping the first and second clock signals to provide the first clock signal on the second channel and the second clock signal on the first channel; determining, based on a comparison of at least one value of the reference signal sampled by the first clock signal to at least two values of the reference signal sampled by the second clock signal, a skew of the second channel; and applying at least one second adjustment factor to the second channel based on the determined skew of the second channel.