Multi-gate thin film transistor, array substrate and display device

摘要

The present invention discloses a multi-gate thin film transistor for realizing a multi-gate occupying a small area, pixels provided with the multi-gate TFTs are high in aperture ratio, and a display device provided with the multi-gate TFTs is high in resolution. The multi-gate thin film transistor comprises: at least three gate electrodes; a plurality of active layers corresponding to each of the gate electrodes, respectively, the active layers being formed into an integrated structure; a source electrode connected with one of the plurality of active layers; and a plurality of drain electrodes connected with each of the remainder of the plurality of active layers, respectively. The present invention further discloses an array substrate comprising the multi-gate thin film transistor, and a display device.

主权项

1. A multi-gate thin film transistor, comprising:
at least three gate electrodes; a plurality of active layers corresponding to each of the gate electrodes, respectively, the active layers being formed into an integrated structure; a source electrode connected with one of the plurality of active layers; and a plurality of drain electrodes connected with each of the rest of the plurality of active layers, respectively, the plurality of drain electrodes being not connected to each other directly, and the active layers being provided between the drain electrodes, wherein, when the multi-gate thin film transistor is turned on, the multi-gate thin film transistor is equivalent to at least two double-gate thin film transistors, and when the multi-gate thin film transistor is turned off, there is no signal crosstalk between the plurality of drain electrodes of the multi-gate thin film transistor, wherein the at least three gate electrodes comprise a first gate electrode, a second gate electrode, a third gate electrode and a fourth gate electrode, and wherein the plurality of active layers comprise a first active layer, a second active layer, a third active layer and a fourth active layer corresponding to the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode, respectively.