发明名称 |
Semiconductor device and method for fabricating the same |
摘要 |
A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure. |
申请公布号 |
US9553143(B2) |
申请公布日期 |
2017.01.24 |
申请号 |
US201514620993 |
申请日期 |
2015.02.12 |
申请人 |
Vanguard International Semiconductor Corporation |
发明人 |
Tu Shang-Hui;Chin Yu-Lung;Lin Shin-Cheng |
分类号 |
H01L29/06;H01L29/423;H01L29/78;H01L29/66 |
主分类号 |
H01L29/06 |
代理机构 |
Birch, Stewart, Kolasch & Birch, LLP |
代理人 |
Birch, Stewart, Kolasch & Birch, LLP |
主权项 |
1. A semiconductor device, comprising:
a semiconductor substrate; a semiconductor layer disposed over the semiconductor substrate; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer, being adjacent to the first well region; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the first and second well regions, between the first and second isolation elements, and having a zig-zag like shape or a U-like shape, wherein the gate structure comprises a gate insulating layer and a conductive layer overlaying the gate insulating layer, a bottom surface of the conductive layer is above a bottom surface of the first well region and a bottom surface of the second well region, and the bottom surface of the conductive layer is below a top surface of the first well region and a top surface of the second well region; a first doped region disposed in the first well region; and a second doped region disposed in the second well region, wherein the semiconductor substrate, the semiconductor layer, and the second well region have a first conductivity type, and the first well region, the first doped region, and the second doped region have a conductivity type that is opposite to the first conductivity type, and a bottom surface of the gate structure is above, lower than or level with a bottom surface of the first isolating element. |
地址 |
Hsinchu TW |