Systems and methods for clock and data recovery

摘要

Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.

主权项

1. An apparatus comprising:
a signal processing circuit configured to acquire phase lock to an input signal in a first mode and to track the input signal in a second mode; and a reset circuit configured to:
count cycles of a first clock signal between edges of the input signal to generate a count; andreset the signal processing circuit when the count is indicative of an absence of the input signal and while the signal processing circuit is in the first mode.