Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity

摘要

The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

主权项

1. A method of semiconductor device fabrication, comprising:
receiving an integrated circuit (IC) layout pattern including a plurality of templates, wherein each template includes a portion of the IC layout pattern; determining a pattern density (PD) for each template of the plurality of templates, wherein the determining the PD provides a first range of pattern densities; identifying, from the plurality of templates, a first template having a first layout pattern with a first PD and a second template having a second layout pattern with a second PD less than the first PD; splitting the first template into a plurality of subset templates, wherein each subset template of the plurality of subset templates includes a portion of the first layout pattern; performing a PD uniformity (PDU) optimization to the second template; and performing multiple individual electron beam (e-beam) lithography exposure processes to a semiconductor substrate, using respective ones of the subset templates, thereby patterning the semiconductor substrate.