Clock mode determination in a memory system

摘要

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

主权项

1. A system comprising:
a memory controller; and at least one non-volatile memory device communicatively coupled to the memory controller, the non-volatile memory device comprising: a non-volatile memory array; a mode selection circuit to put the non-volatile memory device in either a first mode of operation or a second mode of operation; a reference voltage input terminal configured to receive a reference voltage; a first clock terminal configured to receive a positive clock signal; a second clock terminal configured to receive a negative clock signal; a common address and data terminal configured to receive a data input signal that include write data to be programmed into the non-volatile memory array; a data input buffer including a first comparator circuit to receive the data input signal and the reference voltage, and
i) when the non-volatile memory device is in the first mode of operation, the data input buffer is configured to compare the data input signal to the reference voltage in providing a buffered data input signal; andii) when the non-volatile memory device is in the second mode of operation, the data input buffer is configured to provide the buffered data input signal independent of the reference voltage; and a clock input buffer including a second comparator circuit to receive the positive clock signal and the negative clock signal, and
i) when the non-volatile memory device is in the first mode of operation, the clock input buffer is configured to compare the positive clock signal and the negative clock signal in providing a buffered clock input signal; andii) when the non-volatile memory device is in the second mode of operation, the clock input buffer is configured to provide the buffered clock input signal based on either the positive clock input signal or the negative clock input signal.