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1. A scan driving circuit for oxide semiconductor thin film transistors, comprising: a plurality of GOA (Gate Drive On Array) units which are cascade connected, and N is set to be a positive integer and the Nth GOA unit comprises a pull-up control part, a pull-up part, a transfer part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part;
the pull-up control part comprises an eleventh transistor, and a gate of the eleventh transistor is electrically coupled to a driving output end of a N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to an output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a source is electrically coupled to a first node; the first pull-down part comprises a forty-first transistor, and a gate of the forty-first transistor is electrically coupled to a M+2 set clock signal, and a drain is electrically coupled to the first node, and a source is electrically coupled to a second negative voltage level or an output end; the pull-down holding part comprises: a first pull-down holding module and a second pull-down holding module, and the first pull-down holding module and the second pull-down holding module alternately work; the first pull-down holding module comprises a fifty-first transistor, and both a gate and a drain of the fifty-first transistor are electrically coupled to a first low frequency clock signal source, and a source is electrically coupled to a sixth node; a fifty-second transistor, and a gate of the fifty-second transistor is electrically coupled to the first node, and a drain is electrically coupled to the sixth node, and a source is electrically coupled to a first negative voltage level; a fifty-third transistor, and a gate of the fifty-third transistor is electrically coupled to the sixth node, and a drain is electrically coupled to the first low frequency clock signal source, and a source is electrically coupled to a second node; a fifty-fourth transistor, and a gate of the fifty-fourth transistor is electrically coupled to the first node, and a drain is electrically coupled to the second node, and a source is electrically coupled to a third node; a seventy-third transistor and a gate of the seventy-third transistor is electrically coupled to the sixth node and a drain is electrically coupled to the first low frequency clock signal source, and a source is electrically coupled to the third node; a seventy-fourth transistor and a gate of the seventy-fourth transistor is electrically coupled to the first node, and a drain is electrically coupled to the third node, and a source is electrically coupled to a constant low voltage level; a forty-second transistor, and a gate the forty-second transistor is electrically coupled to the second node, and drain is electrically coupled to the first node, and a source is electrically coupled to the second negative voltage level; a thirty-second transistor, and a gate of the thirty-second transistor is electrically coupled to the second node, and a drain electrically coupled to the output end, and a source is electrically coupled to the first negative voltage level; the fifty-first transistor, the fifty-second transistor, the fifty-third transistor the fifty-fourth transistor construct a first main inverter, and the first main inverter is employed to control the thirty-second transistor and the forty-second transistor; the seventy-third transistor and the seventy-fourth transistor construct a first auxiliary inverter, and the first auxiliary inverter is employed to provide low voltage level to the first main inverter in a functioning period, and a high voltage level to the first main inverter in a non-functioning period; the second pull-down holding module comprises a sixty-first transistor, and both a gate and a drain of the sixty-first transistor are electrically coupled a second low frequency clock signal source, and a source is electrically coupled to a seventh node; a sixty-second transistor, and a gate of the sixty-second transistor is electrically coupled to the first node, and a drain is electrically coupled to the seventh node, and a source is electrically coupled to a first negative voltage level; a sixty-third transistor, and a gate of the sixty-third transistor is electrically coupled to the seventh node, and a drain is electrically coupled to the second low frequency clock signal source, and a source electrically coupled to the fourth node; a sixty-fourth transistor, and a gate of the sixty-fourth transistor is electrically coupled to the first node, and a drain is electrically coupled to the fourth node, and a source is electrically coupled to a fifth node; a eighty-third transistor, and a gate of the eighty-third transistor is electrically coupled to the seventh node, and a drain is electrically coupled to the second low frequency clock signal source, and a source is electrically coupled to the fifth node; a eighty-fourth transistor, and a gate of the eighty-fourth transistor is electrically coupled to the first node, and a drain is electrically coupled to the fifth node, and a source is electrically coupled to a constant low voltage level; a forty-third transistor, and a gate of the forty-third transistor is electrically coupled to the fourth node, and a drain is electrically coupled to the first node, and a source is electrically coupled to the second negative voltage level; a thirty-third transistor, and a gate of the thirty-third transistor is electrically coupled to the fourth node, and a drain is electrically coupled to the output end, and a source is electrically coupled to the first negative voltage level; the sixty-first transistor, the sixty-second transistor, the sixty-third transistor, the sixty-fourth transistor construct a second main inverter, and the second main inverter is employed to control the thirty-third transistor and the forty-third transistor; the eighty-third transistor and the eighty-fourth transistor construct a second auxiliary inverter, and the second auxiliary inverter is employed to provide a low voltage level to the second main inverter in a functioning period, and a high voltage level to the second main inverter in a non-functioning period; a relation of the first negative voltage level, the second negative voltage level and the constant low voltage level is: the constant low voltage level<the second negative voltage level<the first negative voltage level. |
