发明名称 |
Trench formation with CD less than 10nm for replacement fin growth |
摘要 |
Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs. |
申请公布号 |
US9553147(B2) |
申请公布日期 |
2017.01.24 |
申请号 |
US201514673033 |
申请日期 |
2015.03.30 |
申请人 |
APPLIED MATERIALS, INC. |
发明人 |
Zhang Ying;Chung Hua |
分类号 |
H01L21/302;H01L29/10;H01L29/66;H01L21/02;H01L21/265;H01L21/3105;H01L21/311 |
主分类号 |
H01L21/302 |
代理机构 |
Patterson & Sheridan, LLP |
代理人 |
Patterson & Sheridan, LLP |
主权项 |
1. A method of forming a semiconducting fin structure, comprising:
etching a first layer to form a feature bounded by a first material; depositing a second layer over the first material and the feature formed in the first layer; etching the second layer to expose a portion of the first layer within the feature through the second layer; and forming a III-V material on the exposed portion of the first layer, the III-V material filling the feature between the second layer. |
地址 |
Santa Clara CA US |